This application relies for priority upon Korean Patent Application No. 2001-28369, filed on May 23, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a method of fabricating a semiconductor device having a gate all around(GAA) structure transistor.
As semiconductor devices become more highly integrated, a number of methods have been developed in order to reduce the sizes of individual devices formed on the semiconductor substrate, and also maximize device performance. Two of the many methods are more common than the others. A first method employs a silicon on insulator (SOI) type substrate, and another method involves forming a three-dimensional device, such as a vertical transistor.
In the first case of using the SOI type substrate, it is possible to perfectly isolate devices, thereby preventing neighboring devices from affecting each other in a highly integrated configuration. Further, the method of using the SOI type substrate provides higher electric pressure resistivity than the method of using device region isolation of a junction, and can reduce the problem of current generation at the junction in an environment of high radiation.
As a representative approach for forming the three-dimensional device, there is the gate all around(GAA) structure. According to the GAA structure, an active region pattern is conventionally formed of a SOI layer on an SOI type substrate. A gate electrode layer is formed to surround a channel portion of the active region pattern covered with a gate insulation layer at a gate electrode. U.S. Pat. No. 5,120,666 and U.S. Pat. No. 5,308,999 disclose a method of fabricating the GAA structure transistor.
In the channel, the entire peripheral portion of the channel surrounded by the gate electrode can be used as a channel, and thus, the effective channel width is increased. Thus, it is possible to solve the problem that the channel width decreases according to the reduction of a device region, thereby decreasing current quantity in a conventional transistor. Also, a channel depletion area formed at the channel peripheral portion can be overlapped and thus, the total channel can form a perfect depletion area.
However, in order to form the GAA structure transistor, a gate electrode should be formed upward and downward the active layer pattern. In forming such a structure, a complex fabrication procedure is required as compared to that of a conventional MOS transistor. Thus, there is a problem that the process becomes complicated and the process expense increases.
Therefore, it is an object of the present invention to provide a method of fabricating a semiconductor device having a GAA structure transistor, where the transistor device has an effect of widening a channel width.
It is another object of the present invention to provide a method of fabricating a semiconductor device having a GAA structure transistor device, where the method can reduce the number of photo-lithography process to simplify the process in order to reduce process complexity when the GAA structure transistor is formed.
The object can be achieved by a method of fabricating a semiconductor device according to the present invention. The method includes the following steps. That is, a SOI substrate composed of a SOI layer, a buried oxide layer, and a bottom substrate layer is prepared. The SOI layer is patterned to form an active layer pattern. An etch stopping layer having an etch selectivity with respect to the buried oxide layer and the active layer pattern is stacked on the active layer pattern. The etch stopping layer is patterned and removed at the gate region that crosses the active layer pattern at the channel region, to form an etch stopping layer pattern and to expose the buried oxide layer. The buried oxide layer is isotropically etched using the etch stopping layer pattern as an etch mask to form a cavity at the channel region beneath the active layer pattern. A conductive material fills the cavity and the space between the etch stopping layer pattern at the gate region.
In the present invention, the active layer pattern and the conductive material filling the cavity should be electrically isolated. In order to isolate the active layer pattern from the conductive material, after the step of forming the cavity, a gate insulation layer may be formed. Also, in the event that the surface of the active layer pattern is thermal-oxidized or thermal-nitrified to form an insulation layer before stacking the etch stopping layer, the gate insulation layer should be formed at the insulation layer-removed part, that is, at the channel region surface of the active layer pattern, until the step of forming the cavity in order to compensate the insulation layer-removed part. Thus, thickness and composition of the insulation layer formed on the surface of the active layer pattern can be different from those of the insulation layer formed on the surfaces of the source/drain regions and the channel region, respectively.